general description the ds8500 is a single-chip modem with highway addressable remote transducer (hart) capabilities and satisfies the hart physical layer requirements. the device integrates the modulation and demodulation of the 1200hz/2200hz fsk signal, has very low power consumption, and needs only a few external compo- nents due to the integrated digital signal processing. the input signal is sampled by an analog-to-digital con- verter (adc), followed by a digital filter/demodulator. this architecture ensures reliable signal detection in noisy environments. the output digital-to-analog con- verter (dac) generates a sine wave and provides a clean signal with phase-continuous switching between 1200hz and 2200hz. low power is achieved by dis- abling the receive circuits during transmit and vice versa. the ds8500 is ideal for low-power process con- trol transmitters. applications 4?0ma loop-powered transmitters for temperature, pressure, flow, and level measurement hart multiplexers hart modem interface connectivity features ? single-chip, half-duplex, 1200bps fsk modulation and demodulation ? digital signal processing provides reliable input signal detection in noisy conditions ? sinusoidal output signal with lowest harmonic distortion ? few external components enable a space-saving solution ? standard component 3.6864mhz crystal ? complies to hart physical layer requirements ? 2.7v to 3.6v operating voltage ? 285? (max) current consumption ? space-saving, 5mm x 5mm x 0.8mm, 20-pin tqfn package ds8500 hart modem ________________________________________________________________ maxim integrated products 1 thin qfn (5mm top view 19 20 18 17 7 6 8 dvdd rst ocd 9 dvdd fsk_in fsk_out avdd agnd 12 dgnd 45 15 14 12 11 d_out d_in dgnd xtal2 xtal1 rts dgnd ref 3 13 dgnd 16 10 xcen dgnd ds8500 + *ep *exposed pad. pin configuration ordering information rev 1; 2/09 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available part temp range pin-package ds8500-jnd+ -40 c to +85 c 20 tqfn-ep* + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed pad.
ds8500 hart modem 2 _______________________________________________________________________________________ absolute maximum ratings recommended dc operating conditions (v dvdd = v avdd = 2.7v to 3.6v, t a = -40? to +85?.) (note 1) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 1: specifications to -40? are guaranteed by design and are not production tested. note 2: active currents are measured when the device is driven by an external clock xcen = 1 condition. note 3: guaranteed by design and not production tested. note 4: accuracy is guaranteed based on the external crystal or clock provided. voltage range on all pins (including avdd, dvdd) relative to ground .................................-0.5v to +3.6v voltage range on any pin relative to ground except avdd, dvdd .............-0.5v to (v dvdd + 0.5v) operating temperature range ...........................-40 c to +85 c storage temperature range .............................-65 c to +150 c soldering temperature...........................refer to the ipc/jedec j-std-020 specification. parameter symbol conditions min typ max units digital supply voltage v dvdd 2.7 3.6 v analog supply voltage v avdd v avdd = v dvdd 2.7 3.6 v ground gnd agnd = dgnd 0 0 v digital power-fail reset voltage v rst monitors v dvdd 2.59 2.64 2.69 v active current i dd v avdd = v dvdd = 2.7v (note 2) 285 a input low voltage v il dgnd 0.30 x v dvdd v input high voltage v il 0.75 x v dvdd v dvdd v output low voltage v ol i ol = 4ma dgnd 0.4 v output high voltage v oh i oh = -4ma 0.8 x v dvdd v i/o pin capacitance c io guaranteed by design (note 3) 15 pf rst pullup resistance r rst 19 45 k input leakage current xtal, rst i ilrx -30 +30 a input leakage current all other pins i il -2 +2 a input low current for rst i il1 v in = 0.4v 170 a clock source external clock frequency f hfin -1% 3.6864 +1% mhz voltage reference internal reference voltage v ref 1.23 v fsk input input voltage range at fsk_in 0 v ref v fsk output output voltage at fsk_out v out ac-coupled max 30k load 400 500 600 mv p-p for a mark -1% 1200 +1% frequency of fsk_out (note 4) for a space -1% 2200 +1% hz
ds8500 hart modem _______________________________________________________________________________________ 3 pin description pin name function 1, 2 dvdd digital supply voltage 3, 9, 16, 17, 18 dgnd digital ground 4 rst active-low reset, digital input/output. this pin includes an internal pullup resistor and is driven low as an output when an internal reset condition occurs. 5 ocd carrier detect, digital output. a logic-high indicates a valid carrier detection on fsk_in. ocd = 1 when fsk_in amplitude is greater than 120mv p-p . ocd = 0 when fsk_in amplitude is less than 80mv p-p . 6 rts request to send, digital input. when set high, the device is put into the demodulator mode. a logic-low puts the device into modulator mode. 7 xtal1 crystal pin or input for external clock at 3.6864mhz 8 xtal2 crystal pin or output of the crystal amplifier 10 xcen external clock enable, digital input. when set high, this pin allows the user to drive an external clock signal through xtal1. when in this mode, xtal2 should be left unconnected. an external crystal must be connected between xtal1 and xtal2 when set low. 11 avdd analog supply voltage 12 fsk_out fsk out, analog output. output of the modulator. provides a phase-continuous, fsk-modulated output signal (1200hz and 2200hz output frequencies) to the 4C20ma current loop interface circuit. 13 ref reference, analog output. the internal voltage reference is provided as output. this pin must be connected to a 0.1f capacitor. 14 fsk_in fsk in, analog input. input for the fsk-modulated hart receive signal from the 4C20ma current loop interface circuit. 15 agnd analog ground 19 d_out digital data out, digital output. output from the demodulator. 20 d_in digital data in, digital input. input to the modulator. ep exposed pad. should be connected to ground (dgnd, agnd). block diagram ds8500 crystal oscillator clock generator xtal1 rst avdd agnd dgnd dvdd power monitor xtal2 rx demodulator digital filter sample/hold adc ocd d_out tx modulator rts d_in xcen fsk_in ref dac fsk_out v ref 1.23v
ds8500 introduction to hart hart is a backward-compatible enhancement to exist- ing 4?0ma instrumentation networks that allows two- way, half-duplex, digital communication with a microcontroller-based field device. the digital signal is encoded on top of the existing instrumentation signal. communication is accomplished through a series of commands and responses dependent on the specific protocol and network topology. the ds8500 does not implement any portion of the communication protocol; it only handles the modulation and demodulation of the encoded information. digital data is encoded using fre- quency-shift keying (fsk), which is illustrated in figure 1. a ??is identified as a mark symbol and is represent- ed with a center frequency of 1.2khz. a ??is identified as a space symbol and is represented with a center fre- quency of 2.2khz. this allows a throughput of 1.2kbps, with each symbol occupying an 833? slot. functional description the ds8500 modem chip consists of a demodulator, car- rier detect, digital filter, adc for input signal conversion, a modulator and dac for output signal generation, and receive and transmit state machine blocks to perform the hart communication. the block diagram illustrates the interface between various blocks of circuitry. the input hart signal? noise interference is attenuat- ed by a one-pole highpass filter that is external to the chip; the attenuated signal is digitized by the adc and filtered by the receive state machine. the transmit state machine modulates the input to the hart-compliant signal with the help of the modulator and the dac. modulator the modulator performs the fsk modulation of the digi- tal data at the d_in input. the fsk-modulated sinu- soidal signal is present at the fsk_out output as illustrated in figure 1. the modulator is enabled by rts being a logic-low. the modulation is done between 1200hz (mark) or 2200hz (space) depending on the logic level of the input signal. the modulator preserves a continuous phase when switching between frequencies to minimize the bandwidth of the transmitted signal. figure 2 illustrates an example waveform of the ds8500 in modulate mode. the data to be modulated is pre- sented in a uart format (start, 8 data bits, parity, stop bit) at d_in. fsk_out shows the modulated output. demodulator the demodulator accepts an fsk signal at the fsk_in input and reproduces the original modulating signal at the d_out output. the hart signal should be present- ed as an 11-bit uart character with a start, data, pari- ty, and stop bits for proper operation of the demodulator block. the nominal bit rate of the d_out signal is 1200 bits per second. a simple rc filter is suf- ficient for anti-aliasing. figure 3 illustrates an example waveform of the ds8500 in demodulate mode. applications information figure 4 shows the typical application circuit. as the ds8500 integrates a digital filter, only a simple passive rc filter is required in front of the adc. r3 and c3 implement a lowpass filter with a 10khz cutoff frequen- cy; c2 and r2/r1 implement a highpass filter with a 480hz cutoff frequency. the resistor-divider formed by r1 and r2 provides an input bias voltage of v ref /2 to the adc input (r1 = r2). the output dac provides a sine-wave signal, and c4 provides the ac-coupled signal output from the ds8500. the typical value of c4 can be anything greater than 20nf based on the application. technical support for technical support, go to http://support.maxim- ic.com/micro . hart modem 4 _______________________________________________________________________________________ 1.2khz mark "1" 2.2khz space "0" v t figure 1. hart fsk signal
ds8500 hart modem _______________________________________________________________________________________ 5 d_in fsk_out start parity stop 8-bit data 1200bps/833 s figure 2. actual ds8500 modulator waveform d_out fsk_in start stop 8-bit data 1200bps/833 s one uart character (start, 8 data bits, parity, stop) parity figure 3. actual ds8500 demodulator waveform
ds8500 hart modem 6 _______________________________________________________________________________________ ds8500 crystal oscillator clock generator xtal1 rst avdd power supply 2.7v to 3.6v agnd dgnd dvdd power monitor xtal2 rx demodulator digital filter sample/hold adc ocd d_out tx modulator rts d_in xcen microcontroller fsk_in ref dac fsk_out v ref 1.23v 3.6864mhz 3.6864mhz crystal r1 r2 c1 c3 c2 c4 r3 hart in 4?0ma dac output hart and 4?0ma out figure 4. typical application circuit package type package code document no. 20 tqfn t2055+3 21-0140 package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages .
ds8500 hart modem maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 _____________________ 7 2009 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 10/08 initial release. in the electrical characteristics table, changed the frequency of fsk_out parameter units from khz to hz. 2 1 2/09 added the ep description to the pin description table. 3
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